Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 281)

VHDL Monitor BFM
Monitor BFM Configuration
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 281
April 2014
A monitor BFM has configuration fields that you can set via the set_config() function to
configure timeout factors, setup and hold times, and so on. You can also get the value of a
configuration field via the
get_config() function. The full list of configuration fields is described
in Table 10-2 .
COMBINED_ACCEPTANCE_
CAPABILITY The maximum number of outstanding combined read and
write transactions that can be accepted by the monitor BFM.
This parameter is set with the Qsys Parameter Editor. See
“
Running the Qsys Tool ” on page 356. for details.
Default: 16.
Table 10-2. Monitor BFM Configuration
Configuration Field Description
Timing Variables
AXI4_CONFIG_SETUP_TIME The setup-time prior to the active edge of
ACLK, in units of simulator time-steps
for all signals.
1
Default: 0.
AXI4_CONFIG_HOLD_TIME The hold-time after the active edge of
ACLK, in units of simulator time-steps
for all signals.
1
Default: 0.
AXI4_CONFIG_MAX_TRANSACTION_
TIME_FACTOR The maximum timeout duration for a
read/write transaction in clock cycles.
Default: 100000.
AXI4_CONFIG_BURST_TIMEOUT_FACTOR The maximum delay between the
individual phases of a read/write
transaction in clock cycles. Default:
10000.
AXI4_CONFIG_MAX_LATENCY_AWVALID
_
ASSERTION_TO_AWREADY The maximum timeout duration from the
assertion of AWVALID to the assertion
of AWREADY in clock. periods. Default:
10000.
AXI4_CONFIG_MAX_LATENCY_ARVALID_
ASSERTION_TO_ARREADY The maximum timeout duration from the
assertion of ARVALID to the assertion of
ARREADY in clock periods.
Default:10000.
AXI4_CONFIG_MAX_LATENCY_RVALID_
ASSERTION_TO_RREADY The maximum timeout duration from the
assertion of RVALID to the assertion of
RREADY in clock periods. Default:
10000.
Table 10-1. Signal Parameters (cont.)
Signal Width Parameter Description