Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 117)

SystemVerilog Tutorials
Verifying a Slave DUT
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 117
April 2014
Figure 6-2. master_ready_delay_mode = AXI4_VALID2READY
The nondefault configuration (master_ready_delay_mode = AXI4_TRANS2READY)
corresponds to the delay measured from the completion of a previous transaction phase
(*VALID and *READY both asserted).
Figure 6-3 shows how to achieve a *READY before
*VALID handshake.
Figure 6-3. master_ready_delay_mode = AXI4_TRANS2READY
*VALID
*READY
ACLK
*_valid_delay = 4 *_ready_delay = 2
*VALID
*READY
ACLK
*_valid_delay = 4
*_ready_delay = 2