Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 61)

SystemVerilog Master BFM
execute_write_resp_ready()
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 61
April 2014
execute_write_resp_ready()
This task executes a write response ready by placing the ready argument value onto the
BREADY signal. It will block for one ACLK period.
Example
// Assert and deassert the BREADY signal
forever begin
bfm.execute_write_resp_ready(1'b0);
bfm.wait_on(AXI4_CLOCK_POSEDGE);
bfm.wait_on(AXI4_CLOCK_POSEDGE);
bfm.execute_write_resp_ready(1'b1);
bfm.wait_on(AXI4_CLOCK_POSEDGE);
end
Prototype task automatic execute_write_resp_ready
(
bit ready
);
Arguments ready The value to be placed onto the BREADY signal
Returns None