Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 126)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 126
SystemVerilog Tutorials
Verifying a Master DUT
April 2014
Example 6-12. m_wr_addr_phase_ready_delay
// Variable : m_wr_addr_phase_ready_delay
int m_wr_addr_phase_ready_delay = 2;
m_wr_data_phase_ready_delay
The m_wr_data_phase_ready_delay variable holds the WREADY signal delay. The delay
value extends the length of each write data phase (beat) in a write data burst by a number of
ACLK cycles. The starting point of the delay is determined by the
slave_ready_delay_mode
variable configuration.
Example 6-13 shows the WREADY signal delayed by two ACLK cycles. You can edit this
function to change the WREADY signal delay.
Example 6-13. m_wr_data_phase_ready_delay
// Variable : m_wr_data_phase_ready_delay
int m_wr_data_phase_ready_delay = 2;
set_read_data_valid_delay()
The set_read_data_valid_delay() function, when called, configures the RVALID signal to be
delayed by a number of ACLK cycles with the effect of delaying the start of each read data
phase (beat). The delay value of the RVALID signal is stored in the data_valid_delay
transaction field.
Example 6-14 shows the RVALID signal delay incrementing by an ACLK cycle between each
read data phase for the length of the burst. You can edit this function to change the RVALID
signal delay.
Example 6-14. set_read_data_valid_delay()
// Function : set_read_data_valid_delay
// This is used to set read data phase valid delays to start driving
// read data/response phases after specified delay.
function void set_read_data_valid_delay(axi4_transaction trans);
trans.set_data_valid_delay(2);
endfunction
set_wr_resp_valid_delay()
The set_wr_resp_valid_delay() function, when called, configures the BVALID signal to be
delayed by a number of ACLK cycles with the effect of delaying the start of the write response
phase. The delay value of the BVALID signal is stored in the write_response_valid_delay
transaction field.