Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 136)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 136
SystemVerilog Tutorials
Verifying a Master DUT
April 2014
handle_read_addr_ready()
The handle_read_addr_ready() task handles the ARREADY signal for the read address
channel. In a forever loop, it delays the assertion of the ARREADY signal based on the settings
of the
slave_ready_delay_mode and m_rd_addr_phase_ready_delay . The
handle_read_addr_ready() task code is similar in operation to the handle_write_addr_ready()
task. Refer to “ SystemVerilog AXI4-Lite Slave BFM Test Program ” on page 390 for the
complete handle_read_addr_ready() code listing.
handle_write_data_ready()
The handle_write_data_ready() task handles the WREADY signal for the write data channel. In
a forever loop, it delays the assertion of the WREADY signal based on the settings of the
slave_ready_delay_mode and m_wr_data_phase_ready_delay . The handle_write_data_ready()
task code is similar in operation to the handle_write_addr_ready() task. Refer to
“ SystemVerilog AXI4-Lite Slave BFM Test Program ” on page 390 for the complete
handle_write_data_ready() code listing.