Rainbow Electronics AT91CAP9S250A - Manual (Page 130)

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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
The 2-bit DEFMSTR_TYPE field selects the default master type (no default, last access mas-
ter, fixed default master) whereas the 4-bit FIXED_DEFMSTR field selects a fixed default
master provided that DEFMSTR_TYPE is set to fixed default master. Refer to the
Section
20.5, ”Bus Matrix User Interface”, on page 133 .
20.4 Arbitration
The Bus Matrix provides an arbitration mechanism that allows to reduce latency when conflict
cases occur, basically when two or more masters try to access the same slave at the same
time. One arbiter per AHB slave is provided, arbitrating each slave differently.
The Bus Matrix provides to the user the possibility to choose between 2 arbitration types, and
this for each slave:
1. Round-Robin Arbitration (the default)
2. Fixed Priority Arbitration
This choice is given through the field ARBT of the Slave Configuration Registers
(MATRIX_SCFG).
Each algorithm may be complemented by selecting a default master configuration for each
slave.
When a re-arbitration has to be done, it is realized only under some specific conditions
detailed in the following paragraph.
20.4.1 Arbitration Rules
Each arbiter has the ability to arbitrate between two or more different master’s requests. In
order to avoid burst breaking and also to provide the maximum throughput for slave interfaces,
arbitration may only take place during the following cycles:
1. Idle Cycles: when a slave is not connected to any master or is connected to a master
which is not currently accessing it.
2. Single Cycles: when a slave is currently doing a single access.
3. End of Burst Cycles: when the current cycle is the last cycle of a burst transfer. For
defined length burst, predicted end of burst matches the size of the transfer but is
managed differently for undefined length burst (See “Undefined Length Burst Arbitra-
tion” on page iv.).
4. Slot Cycle Limit: when the slot cycle counter has reach the limit value indicating that
the current master access is too long and must be broken (See “Slot Cycle Limit Arbi-
tration” on page iv.).
20.4.1.1 Undefined Length Burst Arbitration
In order to avoid too long slave handling during undefined length bursts (INCR), the Bus Matrix
provides specific logic in order to re-arbitrate before the end of the INCR transfer.
A predicted end of burst is used as for defined length burst transfer, which is selected between
the following:
1. Infinite: no predicted end of burst is generated and therefore INCR burst transfer will
never be broken.
2. Four beat bursts: predicted end of burst is generated at the end of each four beat
boundary inside INCR transfer.
3. Eight beat bursts: predicted end of burst is generated at the end of each eight beat
boundary inside INCR transfer.