Rainbow Electronics AT91CAP9S250A - Manual (Page 71)

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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
ARM9EJ-S Technical Reference Manual (DDI 0222A).
13.5.3 JTAG Signal Description
• TMS is the Test Mode Select input which controls the transitions of the test interface state
machine.
• TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary
Scan Register, Instruction Register, or other data registers).
• TDO is the Test Data Output line which is used to serially output the data from the JTAG
registers to the equipment controlling the test. It carries the sampled values from the
boundary scan chain (or other JTAG registers) and propagates them to the next chip in the
serial test circuit.
• NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in
ARM cores and used to reset the debug logic. On Atmel ARM926EJ-S-based cores,
NTRST is a Power On Reset output. It is asserted on power on. If necessary, the user can
also reset the debug logic with the NTRST pin assertion during 2.5 MCK periods.
• TCK is the Test Clock input which enables the test interface. TCK is pulsed by the
equipment controlling the test and not by the tested device. It can be pulsed at any
frequency. Note the maximum JTAG clock rate on ARM926EJ-S cores is 1/6th the clock of
the CPU. This gives 5.45 kHz maximum initial JTAG clock rate for an ARM9E running from
the 32.768 kHz slow clock.
• RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better
clock handling by emulators. From some ICE Interface probes, this return signal can be
used to synchronize the TCK clock and take not care about the given ratio between the ICE
Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE
Mode and not in boundary scan mode.
13.5.4 Debug Unit
The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several
debug and trace purposes and offers an ideal means for in-situ programming solutions and
debug monitor communication. Moreover, the association with two peripheral data controller
channels permits packet handling of these tasks with processor time reduced to a minimum.
The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals
that come from the ICE and that trace the activity of the Debug Communication Channel.The
Debug Unit allows blockage of access to the system through the ICE interface.
A specific register, the Debug Unit Chip ID Register, gives information about the product ver-
sion and its internal configuration.
The AT91CAP9 Debug Unit Chip ID value is 0x039A 03A0 on 32-bit width.
For further details on the Debug Unit, see the section “Debug Unit”.
13.5.5 IEEE 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packag-
ing technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE,
EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor
responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not
IEEE 1149.1 JTAG-compliant.