6 functional description, 1 baud rate generator – Rainbow Electronics AT91CAP9S250A User Manual

Page 529

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529

6264A–CAP–21-May-07

AT91CAP9S500A/AT91CAP9S250A

35.6

Functional Description

The USART is capable of managing several types of serial synchronous or asynchronous
communications.

It supports the following communication modes:

• 5- to 9-bit full-duplex asynchronous serial communication

– MSB- or LSB-first

– 1, 1.5 or 2 stop bits

– Parity even, odd, marked, space or none

– By 8 or by 16 over-sampling receiver frequency

– Optional hardware handshaking

– Optional break management

– Optional multidrop serial communication

• High-speed 5- to 9-bit full-duplex synchronous serial communication

– MSB- or LSB-first

– 1 or 2 stop bits

– Parity even, odd, marked, space or none

– By 8 or by 16 over-sampling frequency

– Optional hardware handshaking

– Optional break management

– Optional multidrop serial communication

• RS485 with driver control signal

• ISO7816, T0 or T1 protocols for interfacing with smart cards

– NACK handling, error counter with repetition and iteration limit

• InfraRed IrDA Modulation and Demodulation

• Test modes

– Remote loopback, local loopback, automatic echo

35.6.1

Baud Rate Generator

The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the
receiver and the transmitter.

The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode
Register (US_MR) between:

• the Master Clock MCK

• a division of the Master Clock, the divider being product dependent, but generally set to 8

• the external clock, available on the SCK pin

The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field
of the Baud Rate Generator Register (US_BRGR). If CD is programmed at 0, the Baud Rate
Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and
becomes inactive.

If the external SCK clock is selected, the duration of the low and high levels of the signal pro-
vided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the
signal provided on SCK must be at least 4.5 times lower than MCK.

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