Rainbow Electronics AT91CAP9S250A User Manual
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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
b u f f e r s i s a f u n c t i o n o f D M A C _ C T R L A x . S R C _ D S C R , D M A C _ C F G x . S R C _ R E P ,
DMAC_CTRLAx.DST_DSCR and DMAC_CFGx.DST_REP registers.
26.3.4.6
Suspension of Transfers Between buffers
At the end of every buffer transfer, an end of buffer interrupt is asserted if:
• the channel buffer interrupt is unmasked, DMAC_EBCIMR.BTC[n] = ‘1’, where n is the
channel number.
Note:
The buffer complete interrupt is generated at the completion of the buffer transfer to the
destination.
At the end of a chain of multiple buffers, an end of linked list interrupt is asserted if:
• the channel end of chained buffer interrupt is unmasked, DMAC_EBCIMR.CBTC[n] = ‘1’,
when n is the channel number.
26.3.4.7
Ending Multi-buffer Transfers
All multi-buffer transfers must end as shown in Row 1 of
. At the end of
every buffer transfer, the DMAC samples the row number, and if the DMAC is in Row 1 state,
then the previous buffer transferred was the last buffer and the DMAC transfer is terminated.
F o r r o w s 9 , 1 0 a n d 1 1 o f
T a b l e 2 6 - 1 o n p a g e 2 8 7
, ( D M A C _ D S C R x = 0 a n d
DMAC_CTRLBx.AUTO is set), multi-buffer DMAC transfers continue until the automatic mode is
disabled by writing a ‘1’ in DMAC_CTRLBx.AUTO bit. This bit should be programmed to zero in
the end of buffer interrupt service routine that services the next-to-last buffer transfer. This puts
the DMAC into Row 1 state.
For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared) the user must setup the last buffer
d e s c r i p t o r i n m e m o r y s u c h t h a t b o t h L L I . D M A C _ C T R L B x . S R C _ D S C R a n d
LLI.DMAC_CTRLBx.DST_DSCR are one and LLI.DMAC_DSCRx is set to 0.