Rainbow Electronics AT91CAP9S250A User Manual
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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
3.
Write the starting source address in the DMAC_SADDRx register for channel x.
Note:
The values in the LLI.DMAC_SADDRx register locations of each of the Linked List Items (LLIs)
setup up in memory, although fetched during a LLI fetch, are not used.
4.
Write the channel configuration information into the DMAC_CFGx register for channel
x.
a.
Designate the handshaking interface type (hardware or software) for the source
and destination peripherals. This is not required for memory. This step requires pro-
gramming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates
the hardware handshaking interface to handle source/destination requests for the
specific channel. Writing a ‘0’ activates the software handshaking interface
source/destination requests.
b.
If the hardware handshaking interface is activated for the source or destination
peripheral, assign handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DST_PER bits, respectively.
5.
Make sure that the LLI.DMAC_CTRLBx register locations of all LLIs in memory (except
the last) are set as shown in Row 6 of
while the
LLI.DMAC_CTRLBx register of the last Linked List item must be set as described in
Row 1 of
shows a Linked List example with two
list items.
6.
Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except
the last) are non-zero and point to the next Linked List Item.
7.
Make sure that the LLI.DMAC_DADDRx register location of all LLIs in memory point to
the start destination buffer address proceeding that LLI fetch.
8.
Make sure that the LLI.DMAC_CTLx.DONE field of the LLI.DMAC_CTRLA register
locations of all LLIs in memory is cleared.
9.
If source picture-in-picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the
DMAC_SPIPx register for channel x.
10. If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP is enabled), program
the DMAC_DPIPx register for channel x.
11. Clear any pending interrupts on the channel from the previous DMAC transfer by read-
ing to the DMAC_EBCISR register.
12. Program the DMAC_CTLx, DMAC_CFGx registers according to Row 6 as shown in
.
13. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first
Linked List item.
14. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit where n
is the channel number. The transfer is performed. Make sure that bit 0 of the DMAC_EN
register is enabled.
15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
Note:
The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI. DMAC_LLPx LLI.DMAC_CTRLAx and
LLI.DMAC_CTRLBx registers are fetched. The LLI.DMAC_SADDRx register although fetched is
not used.
16. Source and destination request single and chunk DMAC transactions to transfer the
buffer of data (assuming non-memory peripherals). DMAC acknowledges at the com-
pletion of every transaction (chunk and single) in the buffer and carry out the buffer
transfer.
17. The DMAC_CTRLAx register is written out to system memory. The DMAC_CTRLAx
register is written out to the same location on the same layer
(DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is the location of the
DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer