Rainbow Electronics AT91CAP9S250A - Manual (Page 296)

296
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
Channel Enable in the Channel Status Register (DMAC_CHSR.ENABLE[n]) until it is
disabled, to detect when the transfer is complete. If the DMAC is not in Row 1, the next
step is performed.
6. The DMAC transfer proceeds as follows:
a. If interrupts is un-masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is the channel
number) hardware sets the buffer complete interrupt when the buffer transfer has
completed. It then stalls until the STALLED[n] bit of DMAC_CHSR register is
cleared by software, writing ‘1’ to DMAC_CHER.KEEPON[n] bit where n is the
channel number. If the next buffer is to be the last buffer in the DMAC transfer, then
the buffer complete ISR (interrupt service routine) should clear the automatic mode
bit in the DMAC_CTRLBx.AUTO bit. This puts the DMAC into Row 1 as shown in
Table 26-1 on page 287 . If the next buffer is not the last buffer in the DMAC trans-
fer, then the reload bits should remain enabled to keep the DMAC in Row 4.
b. If the buffer complete interrupt is masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is
the channel number), then hardware does not stall until it detects a write to the
buffer complete interrupt enable register DMAC_EBCIER register but starts the
next buffer transfer immediately. In this case software must clear the automatic
mode bit in the DMAC_CTRLB to put the DMAC into ROW 1 of
Table 26-1 on page
287 before the last buffer of the DMAC transfer has completed. The transfer is sim-
ilar to that shown in Figure 26-10 on page 296 . The DMAC transfer flow is shown in
Figure 26-11 on page 297 .
Figure 26-10. Multi-buffer DMAC Transfer with Source and Destination Address Auto-reloaded
Address of
Source Layer
Address of
Destination Layer
Source Buffers Destination Buffers
BlockN
Block2
Block1
Block0
SADDR DADDR