Table 47-35 – Rainbow Electronics AT91CAP9S250A User Manual
Page 977
977
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
Figure 47-6. DDRSDRC Timings
The timings of the DDR SDRAM controller support the use of LPDDR200 Double Data Rate
Mobile SDRAM in MAX and STH corners.
Notes:
1. Control/Address is the set of following signals: A0-A9, A11-A13, SDCKE, SDCS, RAS, CAS, SDA10, BAx and SDWE.
2. Data out, DQS refer to D0-D7, DQS0 or to D8-D15, DQS1.
3. DQM refers to DQM0 or DQM1.
SDCK
Control, Addresses
SDCKN
DDR
1
DDR
2
DDR
6
DDR
7
Data in
DDR
4
DDR
5
DDR
4
DDR
5
Data out, DQM
DDR
3
DQS out
DQS in
Table 47-35. LPDDR200 Characteristics
Parameter
Symbol
Min
Max
Units
SDCK/SDCKN Clock Period
t
CK
10
ns
SDCK/SDCKN Clock low or high level
t
CL
,t
CH
0.45
0.55
t
CK
Control/Address In Setup
t
IS
1.5
ns
Control/Address In Hold
CH
t
IH
1.5
ns
DQS output access time from SDCK/SDCKN
t
DQSCK
2
7.0
ns
DQS
t
DQSQ
0.7
ns
Data out output hold time from DQS
t
QH
min(t
CL
,t
CH
)-1.0
ns
Data in and DQM
Setup before DQS edge
t
DS
1.1
ns
Data in and DQM
hold after DQS edge
t
DH
1.1
ns