Rainbow Electronics AT91CAP9S250A User Manual
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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
It is assumed that:
1.
The Advanced Interrupt Controller has been programmed, AIC_SVR registers are
loaded with corresponding interrupt service routine addresses and interrupts are
enabled.
2.
The instruction at the ARM interrupt exception vector address is required to work with
the vectoring
LDR PC, [PC, # -&F20]
When nIRQ is asserted, if the bit “I” of CPSR is 0, the sequence is as follows:
1.
The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded
in the Interrupt link register (R14_irq) and the Program Counter (R15) is loaded with
0x18. In the following cycle during fetch at address 0x1C, the ARM core adjusts
R14_irq, decrementing it by four.
2.
The ARM core enters Interrupt mode, if it has not already done so.
3.
When the instruction loaded at address 0x18 is executed, the program counter is
loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following
effects:
– Sets the current interrupt to be the pending and enabled interrupt with the highest
priority. The current level is the priority level of the current interrupt.
– De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR
must be read in order to de-assert nIRQ.
– Automatically clears the interrupt, if it has been programmed to be edge-triggered.
– Pushes the current level and the current interrupt number on to the stack.
– Returns the value written in the AIC_SVR corresponding to the current interrupt.
4.
The previous step has the effect of branching to the corresponding interrupt service
routine. This should start by saving the link register (R14_irq) and SPSR_IRQ. The
link register must be decremented by four when it is saved if it is to be restored
directly into the program counter at the end of the interrupt. For example, the instruc-
tion
SUB PC, LR, #4
may be used.
5.
Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing re-
assertion of the nIRQ to be taken into account by the core. This can happen if an
interrupt with a higher priority than the current interrupt occurs.
6.
The interrupt handler can then proceed as required, saving the registers that will be
used and restoring them at the end. During this phase, an interrupt of higher priority
than the current level will restart the sequence from step 1.
Note:
If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared
during this phase.
7.
The “I” bit in CPSR must be set in order to mask interrupts before exiting to ensure
that the interrupt is completed in an orderly manner.
8.
The End of Interrupt Command Register (AIC_EOICR) must be written in order to
indicate to the AIC that the current interrupt is finished. This causes the current level
to be popped from the stack, restoring the previous current level if one exists on the
stack. If another interrupt is pending, with lower or equal priority than the old current
level but with higher priority than the new current level, the nIRQ line is re-asserted,
but the interrupt sequence does not immediately start because the “I” bit is set in the
core. SPSR_irq is restored. Finally, the saved value of the link register is restored
directly into the PC. This has the effect of returning from the interrupt to whatever was