10 dmac channel handler enable register – Rainbow Electronics AT91CAP9S250A User Manual
Page 320
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320
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
26.5.10
DMAC Channel Handler Enable Register
Name: DMAC_CHER
Access: Write-only
Reset Value: 0x00000000
• ENA[3:0]
When set, a bit of the ENA field enables the relevant channel.
• SUSP[3:0]
When set, a bit of the SUSPfield freezes the relevant channel and its current context.
• KEEP[3:0]
When set, a bit of the KEEP field resumes the current channel from an automatic stall state.
31
30
29
28
27
26
25
24
–
–
–
–
KEEP3
KEEP2
KEEP1
KEEP0
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
SUSP3
SUSP2
SUSP1
SUSP0
7
6
5
4
3
2
1
0
–
–
–
–
ENA3
ENA2
ENA1
ENA0
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