Rainbow Electronics AT91CAP9S250A - Manual (Page 184)

184
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
22.8.6 Reset Values of Timing Parameters
Table 22-5 gives the default value of timing parameters at reset.
22.8.7 Usage Restriction
The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP
and PULSE parameters is larger than the corresponding CYCLE parameter, this leads to unpre-
dictable behavior of the SMC.
For read operations:
Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the
memory interface because of the propagation delay of theses signals through external logic and
pads. If positive setup and hold values must be verified, then it is strictly recommended to pro-
gram non-null values so as to cover possible skews between address, NCS and NRD signals.
For write operations:
If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address,
byte select lines, and NCS signal after the rising edge of NWE. This is true for WRITE_MODE =
1 only. See
“Early Read Wait State” on page 185 .
For read and write operations: a null value for pulse parameters is forbidden and may lead to
unpredictable behavior.
In read and write cycles, the setup and hold time parameters are defined in reference to the
address bus. For external devices that require setup and hold time between NCS and NRD sig-
nals (read), or between NCS and NWE signals (write), these setup and hold times must be
converted into setup and hold times in reference to the address bus.
22.9 Automatic Wait States
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to
avoid bus contention or operation conflict.
22.9.1 Chip Select Wait States
The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle
cycle ensures that there is no bus contention between the de-activation of one device and the
activation of the next one.
During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to
NWR3, NCS[0..5], NRD lines are all set to 1.
Figure 22-16 illustrates a chip select wait state between access on Chip Select 0 and Chip
Select 2.
Table 22-5. Reset Values of Timing Parameters
Register Reset Value
SMC_SETUP 0X01010101 All setup timings are set to 1
SMC_PULSE 0X01010101 All pulse timings are set to 1
SMC_CYCLE 0X00030003
The read and write operation last 3 Master Clock
cycles and provide one hold cycle
WRITE_MODE 1 Write is controlled with NWE
READ_MODE 1 Read is controlled with NRD