Rainbow Electronics AT91CAP9S250A - Manual (Page 393)

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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
1. The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded
in the FIQ link register (R14_FIQ) and the program counter (R15) is loaded with
0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts
R14_fiq, decrementing it by four.
2. The ARM core enters FIQ mode.
3. When the instruction loaded at address 0x1C is executed, the program counter is
loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automat-
ically clearing the fast interrupt, if it has been programmed to be edge triggered. In
this case only, it de-asserts the nFIQ line on the processor.
4. The previous step enables branching to the corresponding interrupt service routine. It
is not necessary to save the link register R14_fiq and SPSR_fiq if nested fast inter-
rupts are not needed.
5. The Interrupt Handler can then proceed as required. It is not necessary to save regis-
ters R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to
R13 are banked. The other registers, R0 to R7, must be saved before being used,
and restored at the end (before the next step). Note that if the fast interrupt is pro-
grammed to be level sensitive, the source of the interrupt must be cleared during this
phase in order to de-assert the interrupt source 0.
6. Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four
(with instruction
SUB PC, LR, #4 for example). This has the effect of returning
from the interrupt to whatever was being executed before, loading the CPSR with the
SPSR and masking or unmasking the fast interrupt depending on the state saved in
the SPSR.
Note: The “F” bit in SPSR is significant. If it is set, it indicates that the ARM core was just about to
mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is
restored, the interrupted instruction is completed (FIQ is masked).
Another way to handle the fast interrupt is to map the interrupt service routine at the address
of the ARM vector 0x1C. This method does not use the vectoring, so that reading AIC_FVR
must be performed at the very beginning of the handler operation. However, this method
saves the execution of a branch instruction.
30.7.4.5 Fast Forcing
The Fast Forcing feature of the advanced interrupt controller provides redirection of any nor-
mal Interrupt source on the fast interrupt controller.
Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable Register
(AIC_FFER) and the Fast Forcing Disable Register (AIC_FFDR). Writing to these registers
results in an update of the Fast Forcing Status Register (AIC_FFSR) that controls the feature
for each internal or external interrupt source.
When Fast Forcing is disabled, the interrupt sources are handled as described in the previous
pages.
When Fast Forcing is enabled, the edge/level programming and, in certain cases, edge detec-
tion of the interrupt source is still active but the source cannot trigger a normal interrupt to the
processor and is not seen by the priority handler.
If the interrupt source is programmed in level-sensitive mode and an active level is sampled,
Fast Forcing results in the assertion of the nFIQ line to the core.
If the interrupt source is programmed in edge-triggered mode and an active edge is detected,
Fast Forcing results in the assertion of the nFIQ line to the core.