Rainbow Electronics AT91CAP9S250A - Manual (Page 211)

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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
23. DDR/SDR SDRAM Controller (DDRSDRC)
23.1 Description
The DDR/SDR SDRAM Controller (DDRSDRC) is a multiport memory controller. It comprises
four slave AHB interfaces. All simultaneous accesses (four independent AHB ports) are inter-
leaved to maximize memory bandwidth and minimize transaction latency due to SDRAM
protocol.
The DDRSDRC extends the memory capabilities of a chip by providing the interface to an exter-
nal 16-bit or 32-bit SDR-SDRAM device and external 16-bit DDR-SDRAM device. The page size
supports ranges from 2048 to 16384 and the number of columns from 256 to 4096. It supports
byte (8-bit), half-word (16-bit) and word (32-bit) accesses.
The DDRSDRC supports a read or write burst length of 8 locations which frees the command
and address bus to anticipate the next command, thus reducing latency imposed by the SDRAM
protocol and improving the SDRAM bandwidth. Moreover it keeps track of the active row in each
bank, thus maximizing SDRAM performance, e.g., the application may be placed in one bank
and data in the other banks. So as to optimize performance, it is advisable to avoid accessing
different rows in the same bank. The DDRSDRC supports a CAS latency of 2, 2.5 or 3 and opti-
mizes the read access depending on the frequency.
The features of self refresh, power-down and deep power-down modes minimize the consump-
tion of the SDRAM device.
The DDRSDRC user interface is compliant with ARM Advance Peripheral Bus (APB rev2).