Rainbow Electronics AT91CAP9S250A - Manual (Page 918)

918
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
45.3.4.3 Memory Interface
Preview datapath contains a data formatter that converts 8:8:8 pixel to RGB 5:5:5 format compli-
ant with 16-bit format of the LCD controller. In general, when converting from a color channel
with more bits to one with fewer bits, formatter module discards the lower-order bits. Example:
Converting from RGB 8:8:8 to RGB 5:6:5, it discards the three LSBs from the red and blue chan-
nels, and two LSBs from the green channel. When grayscale mode is enabled, two memory
format are supported. One mode supports 2 pixels per word, and the other mode supports 1
pixel per word.
45.3.4.4 FIFO and DMA Features
Both preview and Codec datapaths contain FIFOs, asynchronous buffers that are used to safely
transfer formatted pixels from Pixel clock domain to AHB clock domain. A video arbiter is used to
manage FIFO thresholds and triggers a relevant DMA request through the AHB master inter-
face. Thus, depending on FIFO state, a specified length burst is asserted. Regarding AHB
master interface, it supports Scatter DMA mode through linked list operation. This mode of oper-
ation improves flexibility of image buffer location and allows the user to allocate two or more
frame buffers. The destination frame buffers are defined by a series of Frame Buffer Descriptors
(FBD). Each FBD controls the transfer of one entire frame and then optionally loads a further
FBD to switch the DMA operation at another frame buffer address. The FBD is defined by a
series of two words. The first one defines the current frame buffer address, and the second
defines the next FBD memory location. This DMA transfer mode is only available for preview
datapath and is configured in the ISI_PPFBD register that indicates the memory location of the
first FBD.
The primary FBD is programmed into the camera interface controller. The data to be transferred
described by an FBD requires several burst access. In the example below, the use of 2 ping-
pong frame buffers is described.
Example
The first FBD, stored at address 0x30000, defines the location of the first frame buffer.
Destination Address: frame buffer ID0 0x02A000
Next FBD address: 0x30010
Second FBD, stored at address 0x30010, defines the location of the second frame buffer.
Destination Address: frame buffer ID1 0x3A000
Transfer width: 32 bit
Next FBD address: 0x30000, wrapping to first FBD.
Using this technique, several frame buffers can be configured through the linked list. Figure 45-6
illustrates a typical three frame buffer application. Frame n is mapped to frame buffer 0, frame
n+1 is mapped to frame buffer 1, frame n+2 is mapped to Frame buffer 2, further frames wrap. A
codec request occurs, and the full-size 4:2:2 encoded frame is stored in a dedicated memory
space.
Table 45-8. Grayscale Memory Mapping Configuration for 12-bit Data
GS_MODE DATA[31:24] DATA[23:16] DATA[15:8] DATA[7:0]
0 P_0[11:4] P_0[3:0], 0000 P_1[11:4] P_1[3:0], 0000
1 P_0[11:4] P_0[3:0], 0000 0 0