Rainbow Electronics AT91CAP9S250A - Manual (Page 23)

23
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the
Advanced High-performance Bus (AHB) for its Master and Slave interfaces with additional
features.
Decoding breaks up the 4G bytes of address space into 16 banks of 256M bytes. The banks 1 to
7 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to
EBI_NCS5 and EBI_SDDRCS. The bank 0 is reserved for the addressing of the internal memo-
ries, and a second level of decoding provides 1M byte of internal memory area. The banks 8 to
11 are directed to MP Block (Slave 2) and may be used to address external memories. The bank
15 is split into three parts, one reserved for the peripherals that provides access to the Advanced
Peripheral Bus (APB), the two others are directed to MP Block (Slave 3) and may provide
access to the MP Block APB or to other AHB peripherals.
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
Each Master has its own bus and its own decoder, thus allowing a different memory mapping
per Master. However, in order to simplify the mappings, all the masters have a similar address
decoding.
Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are
assigned to the memory space decoded at address 0x0: one for internal boot, one for external
boot and one after remap. Refer to
Table 8-1, “Internal Memory Mapping,” on page 23 for
details.
8.1 Embedded Memories
• 32 Kbyte ROM
– Single Cycle Access at full matrix speed
• 32 Kbyte Fast SRAM
– Single Cycle Access at full matrix speed
• 20 Kbyte MP Block Fast Dual Port RAM (ten 512x36 DPR instances)
– Used as Dual Port RAM completely managed by MP Block
• 32 Kbyte MP Block Fast Single Port RAM (eight 512x72 SPR instances)
– Used as Single Port RAM completely managed by MP Block
8.1.1 Internal Memory Mapping
Table 8-1 summarizes the Internal Memory Mapping, depending on the Remap status and the
BMS state at reset.
Table 8-1. Internal Memory Mapping
Address
REMAP = 0 REMAP = 1
BMS = 0 BMS = 1
0x0000 0000 ROM EBI_NCS0 SRAM
0x0010 0000 SRAM
0x0020 0000 MP Block Slave 0 (hsel[0])
0x0030 0000 MP Block Slave 0 (hsel[1])
0x0040 0000 ROM