Rainbow Electronics AT91CAP9S250A - Manual (Page 392)

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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
being executed before, and of loading the CPSR with the stored SPSR, masking or
unmasking the interrupts depending on the state saved in SPSR_irq.
Note: The “I” bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of
masking an interrupt when the mask instruction was interrupted. Hence, when SPSR is
restored, the mask instruction is completed (interrupt is masked).
30.7.4 Fast Interrupt
30.7.4.1 Fast Interrupt Source
The interrupt source 0 is the only source which can raise a fast interrupt request to the proces-
sor except if fast forcing is used. The interrupt source 0 is generally connected to a FIQ pin of
the product, either directly or through a PIO Controller.
30.7.4.2 Fast Interrupt Control
The fast interrupt logic of the AIC has no priority controller. The mode of interrupt source 0 is
programmed with the AIC_SMR0 and the field PRIOR of this register is not used even if it
reads what has been written. The field SRCTYPE of AIC_SMR0 enables programming the
fast interrupt source to be positive-edge triggered or negative-edge triggered or high-level sen-
sitive or low-level sensitive
Writing 0x1 in the AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt
Disable Command Register) respectively enables and disables the fast interrupt. The bit 0 of
AIC_IMR (Interrupt Mask Register) indicates whether the fast interrupt is enabled or disabled.
30.7.4.3 Fast Interrupt Vectoring
The fast interrupt handler address can be stored in AIC_SVR0 (Source Vector Register 0).
The value written into this register is returned when the processor reads AIC_FVR (Fast Vec-
tor Register). This offers a way to branch in one single instruction to the interrupt handler, as
AIC_FVR is mapped at the absolute address 0xFFFF F104 and thus accessible from the ARM
fast interrupt vector at address 0x0000 001C through the following instruction:
LDR PC,[PC,# -&F20]
When the processor executes this instruction it loads the value read in AIC_FVR in its pro-
gram counter, thus branching the execution on the fast interrupt handler. It also automatically
performs the clear of the fast interrupt source if it is programmed in edge-triggered mode.
30.7.4.4 Fast Interrupt Handlers
This section gives an overview of the fast interrupt handling sequence when using the AIC. It
is assumed that the programmer understands the architecture of the ARM processor, and
especially the processor interrupt modes and associated status bits.
Assuming that:
1. The Advanced Interrupt Controller has been programmed, AIC_SVR0 is loaded with
the fast interrupt service routine address, and the interrupt source 0 is enabled.
2. The Instruction at address 0x1C (FIQ exception vector address) is required to vector
the fast interrupt:
LDR PC, [PC, # -&F20]
3. The user does not need nested fast interrupts.
When nFIQ is asserted, if the bit “F” of CPSR is 0, the sequence is: