Rainbow Electronics AT91CAP9S250A - Manual (Page 901)

901
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
If one toggle sequencing problem occurs among the n-transactions (n = 1, 2 or 3) inside a microframe, then this bit is still
set as long as the current bank contains one “bad” n-transaction. (see
“CURRENT_BANK/CONTROL_DIR: Current
Bank/Control Direction” on page 902 ) As soon as the current bank is relative to a new “good” n-transactions, then this bit is
reset.
Note1: A transaction error occurs when the toggle sequencing does not respect the Universal Serial Bus Specification, Rev
2.0 (5.9.2 High Bandwidth Isochronous endpoints) (Bad PID, missing data....)
Note2: When a transaction error occurs, the user may empty all the “bad” transactions by clearing the Received OUT Data
flag (RX_BK_RDY).
If this bit is reset, then the user should consider that a new n-transaction is coming.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint).
• RX_SETUP/ERR_FL_ISO: Received SETUP/Error Flow
– Received SETUP: (for Control endpoint only)
This bit is set by hardware when a valid SETUP packet has been received from the host.
It is cleared by the device firmware after reading the SETUP data from the endpoint FIFO.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint).
– Error Flow: (for isochronous endpoint only)
This bit is set by hardware when a transaction error occurs.
– Isochronous IN transaction is missed, the micro has no time to fill the endpoint (underflow).
– Isochronous OUT data is dropped because the bank is busy (overflow).
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
• STALL_SNT/ERR_CRISO/ERR_NBTRA: Stall Sent/CRC ISO Error/Number of Transaction Error
– STALL_SNT: (for Control, Bulk and Interrupt endpoints)
This bit is set by hardware after a STALL handshake has been sent as requested by the UDPHS_EPTSTAx register
FRCESTALL bit.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
– ERR_CRISO: (for Isochronous OUT endpoints) (Read-only)
This bit is set by hardware if the last received data is corrupted (CRC error on data).
This bit is updated by hardware when new data is received (Received OUT Data bit).
– ERR_NBTRA: (for High Bandwidth Isochronous IN endpoints)
This bit is set at the end of a microframe in which at least one data bank has been transmitted, if less than the number of
transactions per micro-frame banks (UDPHS_EPTCFGx register NB_TRANS) have been validated for transmission inside
this microframe.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
• NAK_IN/ERR_FLUSH: NAK IN/Bank Flush Error
– NAK_IN:
This bit is set by hardware when a NAK handshake has been sent in response to an IN request from the Host.
This bit is cleared by software.
– ERR_FLUSH: (for High Bandwidth Isochronous IN endpoints)