Rainbow Electronics AT91CAP9S250A - Manual (Page 14)

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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
• VDDIOMPA pins: Power the MP Block I/O A lines; voltage ranges from 1.65V to 3.6V, 1.8V,
2.5V, 3V or 3.3V nominal.
• VDDIOMPB pins: Power the dedicated MP Block I/O B lines; voltage ranges from 1.65V to
3.6V, 1.8V, 2.5V, 3V or 3.3V nominal.
• VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage
range between1.08V and 1.32V, 1.2V nominal.
• VDDPLL pin: Powers the PLL cells; voltage ranges between 3.0V to 3.6V, 3.3V nominal.
• VDDUTMII pin: Powers the UTMI+ interface; voltage ranges from 3.0V to 3.6V, 3.3V nominal.
• VDDUTMIC pin: Powers the UTMI+ core; voltage ranges between 1.08V and 1.32V, 1.2V
nominal.
• VDDUPLL pin: Powers the USB PLL cell; voltage ranges between 1.08V and 1.32V, 1.2V
nominal.
• VDDANA pin: Powers the ADC cell; voltage ranges between 3.0V and 3.6V, 3.3V nominal.
The power supplies VDDIOM, VDDIOP0 and VDDIOP1 are identified in the pinout table and the
multiplexing tables. These supplies enable the user to power the device differently for interfacing
with memories and for interfacing with peripherals.
Ground pins GNDIO are common to VDDIOM, VDDIOP0, VDDIOP1, VDDIOMPA and VDDI-
OMPB pin power supplies. Separated ground pins are provided for VDDCORE, VDDBU,
VDDPLL, VDDUTMII, VDDUTMIC, VDDUPLL and VDDANA. These ground pins are, respec-
tively, GNDBU, GNDOSC, GNDPLL, GNDUTMII, GNDUTMIC, GNDUPLL and GNDANA.
Special GNDTHERMAL ground balls are thermally coupled with package substrate.
5.2 Power Consumption
The AT91CAP9S500A/AT91CAP9S250A consumes about 700 µA (TBC) of static current on
VDDCORE at 25°C. This static current may go up to 7 mA (TBC) if the temperature increases to
85°C.
On VDDBU, the current does not exceed 3 µA(TBC) @25°C, but can rise at up to 20 µA(TBC)
@85°C.
For dynamic power consumption, the AT91CAP9S500A/AT91CAP9S250A consumes a maxi-
mum of 90 mA (TBC) on VDDCORE at typical conditions (1.2V, 25°C, processor running full-
performance algorithm).
5.3 Programmable I/O Lines Power Supplies
The power supply pins VDDIOM, VDDMPIOA and VDDMPIOB accept two voltage ranges. This
allows the device to reach its maximum speed either out of 1.8V or 3.3V external memories.
The target maximum speed is 100 MHz on the pin DDR/SDR and MPIOA or MPIOB pins loaded
with 30 pF for power supply at 1.8V and 50 pF for power supply at 3.3V. The other signals (con-
trol, address and data signals) do not go over 50 MHz.
The voltage ranges are determined by programming registers in the Chip Configuration registers
located in the Matrix User Interface.
At reset, the selected voltage defaults to 3.3V nominal and power supply pins can accept either
1.8V or 3.3V. Obviously, the device cannot reach its maximum speed if the voltage supplied to
the pins is 1.8V only. The user must make sure to program the EBI voltage range before getting
the device out of its Slow Clock Mode.