Rainbow Electronics AT91CAP9S250A - Manual (Page 224)

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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
23.4.3 Refresh (Auto-refresh Command)
An auto-refresh command is used to refresh the DDRSDRC. Refresh addresses are generated
internally by the SDRAM device and incremented after each auto-refresh automatically. The
DDRSDRC generates these auto-refresh commands periodically. A timer is loaded with the
value in the register DDRSDRAMC_TR that indicates the number of clock cycles between
refresh cycles. When the DDRSDRC initiates a refresh of an SDRAM device, internal memory
accesses are not delayed. However, if the CPU tries to access the SDRAM device, the slave
indicates that the device is busy . A request of refresh does not interrupt a burst transfer in
progress.
23.4.4 Power Management
23.4.4.1 Self Refresh Mode
T h i s m o d e i s a c tiv at e d b y s e tt i n g l o w - po w er c om m a n d bit s [ L P C B ] t o ‘ 01 ’ i n t h e
DDRSDRAMC_LPR Register
Self refresh mode is used in power-down mode, i.e., when no access to the SDRAM device is
possible. In this case, power consumption is very low. In self refresh mode, the SDRAM device
retains data without external clocking and provides its own internal clocking, thus performing its
own auto-refresh cycles. All the inputs to the SDRAM device become don’t care except CKE,
which remains low. As soon as the SDRAM device is selected, the DDRSDRC provides a
sequence of commands and exits self refresh mode.
The DDRSDRC re-enables self refresh mode as soon as the SDRAM device is not selected. It is
possible to define when self refresh mode will be enabled by setting the register LPR (see
Sec-
tion 23.6.6 ”DDRSDRC Low-power Register” on page 240 ), timeout command bit:
• 00 = Self refresh mode is enabled as soon as the SDRAM device is not selected
• 01 = Self refresh mode is enabled 64 clock cycles after completion of the last access
• 10 = Self refresh mode is enabled 128 clock cycles after completion of the last access
This controller also interfaces mobile SDRAM. These devices add a new feature: A single quar-
ter, one half quarter or all banks of the SDRAM array can be enabled in self refresh mode.
Disabled banks will be not refreshed in self refresh mode. This feature permits to reduce the self
refresh current. The extended mode register controls this new feature, it include Temperature
Compensated Self Refresh (TSCR), Partial Array Self refresh (PASR) parameters and drives
strength (DS). These paramaters are set during the initialization phase. After initialization, as
soon as PASR/DS/TCSR fields are modified and self-refresh mode is activated, the Extended
Mode Register is accessed automatically and PASR/DS/TCSR bits are updated before any
entry into self refresh mode.
The mobile SDR-SDRAM must remain in self refresh mode for a minimum period of TRAS peri-
ods and may remain in self refresh mode for an indefinite period. (See
Figure 23-12 on page
225 )
The mobile DDR-SDRAM must remain in self refresh mode for a minimum of TRFC periods and
may remain in self refresh mode for an indefinite period.