Rainbow Electronics AT91CAP9S250A - Manual (Page 252)

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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
latency. The BCRAMC supports latency value which is a function of the Cellular Ram version.
The owait signal is monitored to detect a refresh collision. As soon as owait signal is high, data is
transferred out of the device and first data can be read. As the burst length is fixed to continu-
ous, in the case of single access, it has to stop the burst else invalid values could be read. To
interrupt the read operation, BCCS (chip select) must be set to 1 or an initial burst read/write
command can be initiated to interrupt current access if the next access is a Cellular Ram
access.
To initiate a burst access, the BCRAMC uses the transfer type signals provided by the master
requesting the access. If the next access is a sequential read access, reading to the Cellular
Ram device is carried out. If the next access is a read sequential access, but the current access
is to a boundary page, then an automatic page break is inserted and the Cellular Ram controller
generates an initial burst read command to finish the access. To comply with Cellular Ram tim-
ing parameters, additional clock cycles are inserted to check programmed latency. Like a single
access, the owait signal is monitored to detect refresh collision.
The BCRAMC can anticipate 1 or 2 read accesses. In this case tdf_fr_cram is generated to alert
the EBI that data is floating on the bus and that the next external access will be delayed. In the
case of a burst of specified length, accesses are not anticipated, but, if the burst is broken (i.e.,
border, busy mode...)the next access will be treated as an incrementing burst of unspecified
length, and the BCRAMC can anticipate 1 or 2 read accesses. In this case tdf_from_cram is
generated to alert the EBI that data is floating on the bus and that the next external access will
be delayed.
Read accesses to the Cellular Ram are burst oriented, the burst length programmed is continu-
ous burst. This feature makes it possible to start at a specified address and burst through the
entire memory. It is very useful for incrementing burst (INCR/INCR4/INCR8/INCR16), as soon
as the burst command init (latch burst start address) is initiated and latency is checked, at each
BCCK rising a data is read.
In the case of wrapping burst (WRAP4/WRAP8/WRAP16), the addresses can cross the bound-
ary of the current transfer. For example, when a transfer (WRAP4) starts at address 0x0C, the
next access will be 0x00, but for the burst length being programmed to continuous burst, the
next access should be 0x10. The burst does not wrap automatically. The BCRAMC takes this
feature into account and in the case of a transfer starting at address 0x04/0x08/0x0C, two initial
burst read commands will be issued to wrap when the boundary is reached. The last initial burst
read command will be interrupted by BCCS set to high or by another initial burst read/write com-
mand to do the next access in the Cellular Ram device if an access is pending. tdf_fr_cram will
be generated to
alert the EBI that data is floating on the bus.