Rainbow Electronics AT91CAP9S250A - Manual (Page 294)

294
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
Figure 26-9. DMAC Transfer Flow for Source and Destination Linked List Address
26.3.5.4 Multi-buffer Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 10)
1. Read the Channel Enable register to choose an available (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMAC transfer by read-
ing the interrupt status register. Program the following channel registers:
Channel enabled by
software
LLI Fetch
Hardware reprograms
SADDRx, DADDRx, CTRLA/Bx, DSCRx
DMAC buffer transfer
Writeback of HDMA_CTRLAx
register in system memory
Is HDMA in
Row1 of
HDMA State Machine Table?
Channel Disabled by
hardware
Buffer Complete interrupt
generated here
HDMA Transfer Complete
interrupt generated here yes
no