Rainbow Electronics AT91CAP9S250A - Manual (Page 337)

337
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
27.3 Functional Description
27.3.1 Configuration
The PDC channel user interface enables the user to configure and control data transfers for
each channel. The user interface of each PDC channel is integrated into the associated
peripheral user interface.
The user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit
pointers (RPR, RNPR, TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR,
TNCR). However, the transmit and receive parts of each type are programmed differently: the
transmit and receive parts of a full duplex peripheral can be programmed at the same time,
whereas only one part (transmit or receive) of a half duplex peripheral can be programmed at
a time.
32-bit pointers define the access location in memory for current and next transfer, whether it is
for read (transmit) or write (receive). 16-bit counters define the size of current and next trans-
fers. It is possible, at any moment, to read the number of transfers left for each channel.
The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for
each channel. The status for each channel is located in the associated peripheral status regis-
ter. Transfers can be enabled and/or disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS
in the peripheral’s Transfer Control Register.
At the end of a transfer, the PDC channel sends status flags to its associated peripheral.
These flags are visible in the peripheral status register (ENDRX, ENDTX, RXBUFF, and
TXBUFE). Refer to
Section 27.3.3 and to the associated peripheral user interface.
27.3.2 Memory Pointers
Each full duplex peripheral is connected to the PDC by a receive channel and a transmit chan-
nel. Both channels have 32-bit memory pointers that point respectively to a receive area and
to a transmit area in on- and/or off-chip memory.
Each half duplex peripheral is connected to the PDC by a bidirectional channel. This channel
has two 32-bit memory pointers, one for current transfer and the other for next transfer. These
pointers point to transmit or receive data depending on the operating mode of the peripheral.
Depending on the type of transfer (byte, half-word or word), the memory pointer is incre-
mented respectively by 1, 2 or 4 bytes.
If a memory pointer address changes in the middle of a transfer, the PDC channel continues
operating using the new address.
27.3.3 Transfer Counters
Each channel has two 16-bit counters, one for current transfer and the other one for next
transfer. These counters define the size of data to be transferred by the channel. The current
transfer counter is decremented first as the data addressed by current memory pointer starts
to be transferred. When the current transfer counter reaches zero, the channel checks its next
transfer counter. If the value of next counter is zero, the channel stops transferring data and
sets the appropriate flag. But if the next counter value is greater then zero, the values of the
next pointer/next counter are copied into the current pointer/current counter and the channel
resumes the transfer whereas next pointer/next counter get zero/zero as values. At the end of
this transfer the PDC channel sets the appropriate flags in the Peripheral Status Register.