4 functional description, 1 sdram controller write cycle – Rainbow Electronics AT91CAP9S250A User Manual
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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
8.
A Mode Register set (MRS) cycle is issued to program the parameters of the DDR-
SDRAM devices, in particular CAS latency, burst length. The application must set Mode
to 3 in the Mode Register (see
) and perform a write access
to the DDR-SDRAM to acknowledge this command. The write address must be chosen
so that BA[1:0] bits are set to 0. For example, with a 16-bit 128 MB DDR-SDRAM (12
rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at
the address 0x20000000.
9.
The application must go into Normal Mode, setting Mode to 0 in the Mode Register (see
) and performing a write access at any location in the DDR-
SDRAM to acknowledge this command.
10. Perform a write access to any DDR-SDRAM address.
11. Write the refresh rate into the count field in the SDRAMC Refresh Timer register (see
). (Refresh rate = delay between refresh cycles). The DDR-SDRAM device
requires a refresh every 15.625 µs or 7.81 µs. With a 100 MHz frequency, the refresh
timer count register must to be set with (15.625 /100 MHz) = 1562 i.e. 0x061A or (7.81
/100 MHz) = 781 i.e. 0x030d
12. After initialization, the DDR-SDRAM device is fully functional.
23.4
Functional Description
23.4.1
SDRAM Controller Write Cycle
The DDRSDRC allows burst access or single access in normal mode (mode = 000). Whatever
the access type, the DDRSDRC keeps track of the active row in each bank, thus maximizing
performance.
The SDRAM device is programmed with a burst length equal to 8. This determines the length of
a sequential data input by the write command that is set to 8. The latency from write command to
data input is fixed to 1 in the case of DDR-SDRAM devices. In the case of SDR-SDRAM
devices, there is no latency from write command to data input.
To initiate a single access, the DDRSDRC checks if the page access is already open. If
row/bank addresses match with the previous row/bank addresses, the controller generates a
write command. If the bank addresses are not identical or if bank addresses are identical but the
row addresses are not identical, the controller generates a precharge command, activates the
new row and initiates a write command. To comply with SDRAM timing parameters, additional
clock cycles are inserted between precharge/active (t RP) commands and active/write (t RCD)
command. As the burst length is fixed to 8, in the case of single access, it has to stop the burst,
otherwise seven invalid values may be written. In the case of SDR-SDRAM devices, a Burst
Stop command is generated to interrupt the write operation. In the case of DDR-SDRAM
devices, Burst Stop command is not supported for the burst write operation. In order to then
interrupt the write operation, Dm must be set to 1 to mask invalid data (see
and
) and DQS must continue to toggle.
To initiate a burst access, the DDRSDRC uses the transfer type signal provided by the master
requesting the access. If the next access is a sequential write access, writing to the SDRAM
device is carried out. If the next access is a write non-sequential access, then an automatic
access break is inserted, the DDRSDRC generates a precharge command, activates the new
row and initiates a write command. To comply with SDRAM timing parameters, additional clock
cycles are inserted between precharge/active (tRP) commands and active/write (tRCD)
commands.