Rainbow Electronics AT91CAP9S250A - Manual (Page 47)

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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
11.2 External Connectivity
The MPBlock is connected to the following external resources.
11.2.1 Dedicated I/O Lines
The MPBlock is directly connected to 77 (32 MPIOA and 45 MPIOB lines) dedicated I/O Pads
with the following features:
• Supply/Drive control pin (needed for high-speed or low voltage interfaces)
• Pull-up control pin
• Supported logic levels include:
– LVCMOS33 at 100 MHz maximum frequency
– LVCMOS25 at 50 MHz maximum frequency
– LVCMOS18 at 100 MHz maximum frequency
Only 32 dedicated I/O pins are available in the TFBGA324 package.
11.2.2 UTMI+ Transceiver
The MPBlock may be connected to the UTMI+ transceiver. As only one UTMI+ transceiver is
available, the USB High-speed Device and the MPBlock do not have access to the UTMI+ at the
same time. However, a dual role Master-Slave USB High-Speed may be implemented by using
the USB High-speed Device and integrating a High-speed Host in the MPBlock as the switching
between both is generated inside the MPBlock.
11.3 Prototyping Solution
In order to prototype the final custom design, a Prototyping Platform version of the
AT91CAP9S500A/AT91CAP9S250A design has been created. The platform maps APB and
AHB masters or slaves into the FPGA located outside the chip with the following features and
restrictions:
• AT91CAP9S500A/AT91CAP9S250A to FPGA interface is provided to prototype AHB masters
and slave into the external FPGA exactly as if it were in MPBlock.
• Prototyped AHB Masters
– Prototyped AHB Masters have access to AT91CAP9S500A/AT91CAP9S250A slave
resources.
– Prototyped AHB Masters have access to MPBlock (FPGA) slave resources.
• Prototyped AHB Slaves
– Prototyped AHB Slaves may be accessed from AT91CAP9S500A/AT91CAP9S250A
master resources.
– Prototyped AHB Slaves may be accessed from MPBlock (FPGA) resources.
• Prototyped APB Slaves
– APB bus must be created locally in the FPGA by implementing AHB to APB bridge.
Peripheral DMA controller may also be necessary to implement locally in the FPGA
in order to prototype PDC enabled APB peripherals.
Figure 11-2 shows a typical prototyping solution.