Rainbow Electronics AT91CAP9S250A - Manual (Page 155)

155
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
21.5.9 NAND Flash Support
External Bus Interface integrates circuitry that interfaces to NAND Flash devices.
21.5.9.1 External Bus Interface
The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space.
Programming the EBI_CS3A field in the EBI_CSA Register in the Chip Configuration User
Interface to the appropriate value enables the NAND Flash logic.
For details on this register,
refer to Section 20. ”Bus Matrix” on page 129 . Access to an external NAND Flash device is
then made by accessing the address space reserved to NCS3 (i.e., between 0x4000 0000 and
0x4FFF FFFF).
The NAND Flash Logic drives the read and write command signals of the SMC on the NAN-
DOE and NANDWE signals when the NCS3 signal is active. NANDOE and NANDWE are
invalidated as soon as the transfer address fails to lie in the NCS3 address space. See
Figure
21-5 on page 155 for more information. For details on these waveforms, refer to the section
“Static Memory Controller”.
Figure 21-5. NAND Flash Signal Multiplexing on EBI Pins
21.5.9.2 NAND Flash Signals
The address latch enable and command latch enable signals on the NAND Flash device are
driven by address bits A22 and A21 of the EBI address bus. The user should note that any bit
on the EBI address bus can also be used for this purpose. The command, address or data
words on the data bus of the NAND Flash device are distinguished by using their address
within the NCS3 address space. The chip enable (CE) signal of the device and the ready/busy
(R/B) signals are connected to PIO lines. The CE signal then remains asserted even when
NCS3 is not selected, preventing the device from returning to standby mode.
SMC
NRD
NWR0_NWE
NANDOE
NANDWE
NAND Flash Logic
NCS3
NANDWE
NANDOE