Rainbow Electronics AT91CAP9S250A - Manual (Page 129)

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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
20. Bus Matrix
20.1 Description
The Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol, that enables par-
allel access paths between multiple AHB masters and slaves in a system, which increases the
overall bandwidth. Bus Matrix interconnects 12 AHB Masters to
10 AHB Slaves. The normal
latency to connect a master to a slave is one cycle except for the default master of the
accessed slave which is connected directly (zero cycle latency).
The Bus Matrix user interface is compliant with the ARM Advanced Peripheral Bus and pro-
vides a Chip Configuration User Interface with Registers that allow the Bus Matrix to support
application specific features.
20.2 Memory Mapping
The Bus Matrix provides one decoder for every AHB Master Interface. The decoder offers
each AHB Master several memory mappings. In fact, depending on the product, each memory
area may be assigned to several slaves. Booting at the same address while using different
AHB slaves (i.e. external RAM, internal ROM or internal Flash etc.) becomes possible.
The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that
allows to perform remap action for every master independently.
20.3 Special Bus Granting Techniques
The Bus Matrix provides some speculative bus granting techniques in order to anticipate
access requests from some masters. This mechanism allows to reduce latency at first
accesses of a burst or single transfer. The bus granting mechanism allows to set a default
master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected
to its associated default master. A slave can be associated with three kinds of default masters:
no default master, last access master and fixed default master.
20.3.1 No Default Master
At the end of the current access, if no other request is pending, the slave is disconnected from
all masters. No Default Master, suits low power mode.
20.3.2 Last Access Master
At the end of the current access, if no other request is pending, the slave remains connected
to the last master that performed an access request.
20.3.3 Fixed Default Master
At the end of the current access, if no other request is pending, the slave connects to itsfixed
default master. Unlike last access master, the fixed master doesn’t change unless the user
modifies it by a software action (field FIXED_DEFMSTR of the related MATRIX_SCFG).
To change from one kind of default master to another, the Bus Matrix user interface provides
the Slave Configuration Registers, one for each slave, that allow to set a default master for
each slave. The Slave Configuration Register contains two fields:
• DEFMSTR_TYPE and
• FIXED_DEFMSTR