Rainbow Electronics AT91CAP9S250A - Manual (Page 248)

248
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
24.4 Functional Description
24.4.1 BCRAMC Overview
The BCRAMC is a synchronous cellular RAM controller, it does not support asynchronous
access and mode page. Some version 1.0 devices which support only these features cannot be
driven.
The BCRAMC drives 16-bit memory devices but, in this mode, it does not support byte
read/write bursts. All byte burst accesses are treated as a single access because BCRAMC is
set in continuous burst where16-bit data are accessed sequentially. To support byte read/write
bursts, complex logic should be added to transform byte burst to half-word burst.
The BCRAMC drives 32-bit memory devices but, in this mode, it does not support byte/half-word
read/write bursts. All byte or half-word burst accesses are treated as single access because
BCRAMC is set in continuous burst where 32-bit data are accessed sequentially. To support
byte/half-word read/write bursts, complex logic should be added to transform byte/half-word
bursts to word bursts.
The BCRAMC supports busy transfer. This kind of access is treated as early burst termination.
The controller performances are decreased because after a busy transfer, a new initial burst
operation (adv is low) will be generated.
24.4.2 BCRAMC Write Cycle
The BCRAMC provides burst access or single access.
The Cellular Ram device is programmed with a continuous burst length.
The latency from write command to data input is a function of the Cellular Ram device.
Version 1.0 write latency is equal to the latency programmed in the bus configuration register
during the initialization sequence or in the worst case, it is equal to the refresh collision delay.
With version 1.0, the BCRAMC must monitor owait signal to detect any conflict of refresh colli-
sion during write accesses. The write latency is not constant.
In the case of version 1.5 and 2.0, write latency is equal to the latency programmed in the bus
configuration register. Write latency always uses fixed latency. The BCRAMC does not monitor
owait signal during write accesses.
To initiate a single access, the BCRAMC generates an initial burst write command. To comply
with Cellular Ram timing parameters, additional clock cycles are inserted to check programmed
latency. In the case of Cellular Ram version 1.0, the owait signal is monitored to detect a refresh
collision. As soon as owait signal is high, data is accepted into the device and write access is
achieved. In the case of Cellular Ram version 1.5 and 2.0, owait signal is not monitored and
write access is performed as soon as latency is checked.
As the burst length is fixed to continuous, in the case of single access, it has to stop the burst
else invalid values can be written. To interrupt the write operation, chip select (CS) must be set
to 1 or an initial burst read/write command can be initiated to interrupt current access if the next
access is a Cellular Ram access.
To initiate a burst access, the BCRAMC uses the transfer type signal provided by the master
requesting the access. If the next access is a sequential write access, writing to the Cellular
Ram device is carried out. If the next access is a write sequential access, but the current access
is to a boundary page, then an automatic page break is inserted and the Cellular Ram controller
generates an initial burst write command to finish access. To comply with Cellular Ram timing