1 read waveforms – Rainbow Electronics AT91CAP9S250A User Manual
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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
22.8.1
Read Waveforms
The read cycle is shown on
.
The read cycle starts with the address setting on the memory address bus, i.e.:
{A[25:2], A1, A0} for 8-bit devices
{A[25:2], A1} for 16-bit devices
A[25:2] for 32-bit devices.
Figure 22-8. Standard Read Cycle
22.8.1.1
NRD Waveform
The NRD signal is characterized by a setup timing, a pulse width and a hold timing.
1.
NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD
falling edge;
2.
NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD
rising edge;
3.
NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD
rising edge.
A[25:2]
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NCS
NRD_SETUP
NRD_PULSE
NRD_HOLD
MCK
NRD
D[31:0]
NCS_RD_SETUP
NCS_RD_PULSE
NCS_RD_HOLD
NRD_CYCLE