Rainbow Electronics AT91CAP9S250A User Manual
Page 543
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543
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
35.6.3.7
Receiver Operations
When a character reception is completed, it is transferred to the Receive Holding Register
(US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is com-
pleted while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is
transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing
the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1.
Figure 35-21. Receiver Status
D0
D1
D2
D3
D4
D5
D6
D7
RXD
Start
Bit
Parity
Bit
Stop
Bit
Baud Rate
Clock
Write
US_CR
RXRDY
OVRE
D0
D1
D2
D3
D4
D5
D6
D7
Start
Bit
Parity
Bit
Stop
Bit
RSTSTA = 1
Read
US_RHR
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