I/o line considerations, 1 jtag port pins, 2 test pin – Rainbow Electronics AT91CAP9S250A User Manual

Page 15: 3 reset pins, 4 pio controllers, 5 shutdown logic pins

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15

6264A–CAP–21-May-07

AT91CAP9S500A/AT91CAP9S250A

6.

I/O Line Considerations

6.1

JTAG Port Pins

TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors.

TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors.

The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It
integrates a permanent pull-down resistor of about 15 k

to GNDBU so that it can be left uncon-

nected for normal operations.

The NTRST signal is described in

Section 6.3 ”Reset Pins” on page 15

.

All the JTAG signals are supplied with VDDIOP0.

6.2

Test Pin

The TST pin is used for manufacturing test purposes when asserted high. It integrates a perma-
nent pull-down resistor of about 15 k

to GNDBU so that it can be left unconnected for normal

operations. Driving this line at a high level leads to unpredictable results.

This pin is supplied with VDDBU.

6.3

Reset Pins

NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven
with voltage at up to VDDIOP0.

NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the
processor.

As the product integrates power-on reset cells that manage the processor and the JTAG reset,
the NRST and NTRST pins can be left unconnected.

The NRST and NTRST pins both integrate a permanent pull-up resistor of 90 k

minimum to

VDDIOP0.

The NRST signal is inserted in the Boundary Scan.

6.4

PIO Controllers

All the I/O lines which are managed by the PIO Controllers integrate a programmable pull-up
resistor of 90 k

minimum. Programming of this pull-up resistor is performed independently for

each I/O line through the PIO Controllers.

After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those multi-
plexed with the External Bus Interface signals that must be enabled as Peripheral at reset. This
is indicated in the column “Reset State” of the PIO Controller multiplexing tables.

6.5

Shutdown Logic Pins

The SHDN pin is an output only, which is driven by the Shutdown Controller only at low level. It
can be tied high with an external pull-up resistor at VDDBU only.

The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.

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