Rainbow Electronics AT91CAP9S250A - Manual (Page 305)

305
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
the linked list item fetched prior to the start of the buffer transfer. Only DMAC_CTRLAx
register is written out because only the DMAC_CTRLAx.BTSIZE and
DMAC_CTRLAX.DONE fields have been updated by DMAC hardware. Additionally, the
DMAC_CTRLAx.DONE bit is asserted when the buffer transfer has completed.
Note: Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the
LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is
asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared
at the start of the transfer.
18. The DMAC does not wait for the buffer interrupt to be cleared, but continues and
fetches the next LLI from the memory location pointed to by current DMAC_DSCRx
register and automatically reprograms the DMAC_SADDRx, DMAC_CTRLAx,
DMAC_CTRLBx and DMAC_DSCRx channel registers. The DMAC_DADDRx register
is left unchanged. The DMAC transfer continues until the DMAC samples the
DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer
transfer match that described in Row 1 of
Table 26-1 on page 287 . The DMAC then
knows that the previous buffer transferred was the last buffer in the DMAC transfer.
The DMAC transfer might look like that shown in Figure 26-16 on page 305 Note that the desti-
nation address is decrementing.
Figure 26-16. DMAC Transfer with Linked List Source Address and Contiguous Destination Address
The DMAC transfer flow is shown in Figure 26-17 on page 306 .
SADDR(2)
SADDR(1)
SADDR(0)
DADDR(2)
DADDR(1)
DADDR(0)
Buffer 2
Buffer 1
Buffer 0
Buffer 0
Buffer 1
Buffer 2
Address of
Source Layer
Address of
Destination Layer
Source Buffers Destination Buffers