Rainbow Electronics AT91CAP9S250A - Manual (Page 842)

842
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
Memory access errors (abort, misalignment) lead to an “UnrecoverableError” indicated by the
corresponding flag in the host controller operational registers.
The USB root hub is integrated in the USB host. Several USB downstream ports are available.
The number of downstream ports can be determined by the software driver reading the root
hub’s operational registers. Device connection is automatically detected by the USB host port
logic.
USB physical transceivers are integrated in the product and driven by the root hub’s ports.
Over current protection on ports can be activated by the USB host controller. Atmel’s standard
product does not dedicate pads to external over current protection.
43.3 Product Dependencies
43.3.1 I/O Lines
DPs and DMs are not controlled by any PIO controllers. The embedded USB physical transceiv-
ers are controlled by the USB host controller.
43.3.2 Power Management
The USB host controller requires a 48 MHz clock. This clock must be generated by a PLL with a
correct accuracy of ± 0.25%.
Thus the USB device peripheral receives two clocks from the Power Management Controller
(PMC): the master clock MCK used to drive the peripheral user interface (MCK domain) and the
UHPCLK 48 MHz clock used to interface with the bus USB signals (Recovered 12 MHz domain).
43.3.3 Interrupt
The USB host interface has an interrupt line connected to the Advanced Interrupt Controller
(AIC).
Handling USB host interrupts requires programming the AIC before configuring the UHP.
43.4 Functional Description
Please refer to the Open Host Controller Interface Specification for USB Release 1.0.a.
43.4.1 Host Controller Interface
There are two communication channels between the Host Controller and the Host Controller
Driver. The first channel uses a set of operational registers located on the USB Host Controller.
The Host Controller is the target for all communications on this channel. The operational regis-
ters contain control, status and list pointer registers. They are mapped in the memory mapped
area. Within the operational register set there is a pointer to a location in the processor address
space named the Host Controller Communication Area (HCCA). The HCCA is the second com-
munication channel. The host controller is the master for all communication on this channel. The
HCCA contains the head pointers to the interrupt Endpoint Descriptor lists, the head pointer to
the done queue and status information associated with start-of-frame processing.
The basic building blocks for communication across the interface are Endpoint Descriptors (ED,
4 double words) and Transfer Descriptors (TD, 4 or 8 double words). The host controller assigns
an Endpoint Descriptor to each endpoint in the system. A queue of Transfer Descriptors is linked
to the Endpoint Descriptor for the specific endpoint.