Rainbow Electronics AT91CAP9S250A - Manual (Page 226)

226
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
23.4.4.2 Power-down Mode
This mode is activated by setting the low-power command bits [LPCB] to ‘10’.
Power-down mode is used when no access to the SDRAM device is possible. In this mode,
power consumption is greater than in self refresh mode. This state is similar to normal mode (No
low-power mode/No self refresh mode), but the CKE pin is low and the input and output buffers
are deactivated as soon the SDRAM device is no longer accessible. In contrast to self refresh
mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64
ms). As no auto-refresh operations are performed in this mode, the DDRSDRC carries out the
refresh operation. In order to exit low-power mode, a NOP command is required in the case of
Mobile SDR-SDRAM, SDR-SDRAM and DDR-SDRAM devices. In the case of Mobile DDR-
SDRAM devices, the controller generates a NOP command during a delay of at least TXP. In
addition, Mobile DDR-SDRAM must remain in power-down mode for a minimum period of TCKE
periods.
The exit procedure is faster than in self refresh mode. See Figure 23-15 on page 226 . The
DDRSDRAMC returns to power-down mode as soon as the SDRAM device is not selected. It is
possible to define when power-down mode is enabled by setting the register LPR, timeout com-
mand bit.
• 00 = Power-down mode is enabled as soon as the SDRAM device is not selected
• 01 = Power-down mode is enabled 64 clock cycles after completion of the last access
• 10 = Power-down mode is enabled 128 clock cycles after completion of the last access
Figure 23-15. Power-down Entry/Exit, Timeout =0
Entry power down mode Exit power down mode
SDCK
A[12:0]
READ EEPPWD NOP READ COMMAND
CKE
0 BA[1:0]
DQS[1:0]
Da Db D[15:0]
3 DM[1:0]