Rainbow Electronics AT91CAP9S250A - Manual (Page 619)

619
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
37.3 Pin Name List
The AC‘97 reset signal provided to the primary codec can be generated by a PIO.
37.4 Application Block Diagram
Figure 37-2. Application Block diagram
Table 37-1. I/O Lines Description
Pin Name Pin Description Type
AC97CK 12.288-MHz bit-rate clock Input
AC97RX Receiver Data (Referred as SDATA_IN in AC-link spec) Input
AC97FS 48-KHz frame indicator and synchronizer Output
AC97TX Transmitter Data (Referred as SDATA_OUT in AC-link spec) Output
AC 97 Controller
AC97TX
AC97RX
PIOx
AC'97 Primary Codec
AC97FS
AC97CK
AC97_RESET
AC97_SYNC
AC97_SDATA_OUT
AC97_BITCLK
AC-link
AC97_SDATA_IN