Rainbow Electronics AT91CAP9S250A - Manual (Page 864)

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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
– END_BUFFIT: Generate an interrupt when BUFF_COUNT in the
UDPHS_DMASTATUSx register reaches 0.
– END_TR_EN: End of transfer enable, the UDPHS device can put an end to the
current DMA transfer, in case of a short packet.
– END_TR_IT: End of transfer interrupt enable, an interrupt is sent after the last USB
packet has been transferred by the DMA, if the USB transfer ended with a short
packet. (Beneficial when the receive size is unknown.)
– CHANN_ENB: Run and stop at end of buffer.
For OUT transfer, the bank will be automatically cleared by hardware when the application has
read all the bytes in the bank (the bank is empty).
Note: When a zero-length-packet is received, RX_BK_RDY bit in UDPHS_EPTSTAx is cleared
automatically by AUTO_VALID, and the application knows of the end of buffer by the presence
of the END_TR_IT.
Note: If the host sends a zero-length packet, and the endpoint is free, then the device sends an
ACK. No data is written in the endpoint, the RX_BY_RDY interrupt is generated, and the
BYTE_COUNT field in UDPHS_EPTSTAx is null.
Figure 44-12. Data OUT Transfer for Endpoint with One Bank
ACK Token OUT NAK Token OUT ACK Token OUT Data OUT 1
USB Bus
Packets
RX_BK_RDY
Set by Hardware Cleared by Firmware,
Data Payload Written in FIFO
FIFO (DPR)
Content
Written by UDPHS Device Microcontroller Read
Data OUT 1 Data OUT 1 Data OUT 2
Host Resends the Next Data Payload
Microcontroller Transfers Data
Host Sends Data Payload
Data OUT 2 Data OUT 2
Host Sends the Next Data Payload
Written by UDPHS Device
(UDPHS_EPTSTAx)
Interrupt Pending