Rainbow Electronics AT91CAP9S250A User Manual

Page 549

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549

6264A–CAP–21-May-07

AT91CAP9S500A/AT91CAP9S250A

The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK
commands are taken into account only if the TXRDY bit in US_CSR is at 1 and the start of the
break condition clears the TXRDY and TXEMPTY bits as if a character is processed.

Writing US_CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable
result. All STPBRK commands requested without a previous STTBRK command are ignored. A
byte written into the Transmit Holding Register while a break is pending, but not started, is
ignored.

After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times.
Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the
start of the next character. If the timeguard is programmed with a value higher than 12, the TXD
line is held high for the timeguard period.

After holding the TXD line for this period, the transmitter resumes normal operations.

Figure 35-26

illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK)

commands on the TXD line.

Figure 35-26. Break Transmission

35.6.3.14

Receive Break

The receiver detects a break condition when all data, parity and stop bits are low. This corre-
sponds to detecting a framing error with data at 0x00, but FRAME remains low.

When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may
be cleared by writing the Control Register (US_CR) with the bit RSTSTA at 1.

An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchro-
nous operating mode or one sample at high level in synchronous operating mode. The end of
break detection also asserts the RXBRK bit.

35.6.3.15

Hardware Handshaking

The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins
are used to connect with the remote device, as shown in

Figure 35-27

.

D0

D1

D2

D3

D4

D5

D6

D7

TXD

Start

Bit

Parity

Bit

Stop

Bit

Baud Rate

Clock

Write

US_CR

TXRDY

TXEMPTY

STPBRK = 1

STTBRK = 1

Break Transmission

End of Break

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