Rainbow Electronics AT91CAP9S250A - Manual (Page 693)

693
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
Figure 39-7. Line Error Mode
An error active unit takes part in bus communication and sends an active error frame when the
CAN controller detects an error.
An error passive unit cannot send an active error frame. It takes part in bus communication,
but when an error is detected, a passive error frame is sent. Also, after a transmission, an
error passive unit waits before initiating further transmission.
A bus off unit is not allowed to have any influence on the bus.
For fault confinement, two errors counters (TEC and REC) are implemented. These counters
are accessible via the CAN_ECR register. The state of the CAN controller is automatically
updated according to these counter values. If the CAN controller is in Error Active state, then
the ERRA bit is set in the CAN_SR register. The corresponding interrupt is pending while the
interrupt is not masked in the CAN_IMR register. If the CAN controller is in Error Passive
Mode, then the ERRP bit is set in the CAN_SR register and an interrupt remains pending while
the ERRP bit is set in the CAN_IMR register. If the CAN is in Bus-off Mode, then the BOFF bit
is set in the CAN_SR register. As for ERRP and ERRA, an interrupt is pending while the BOFF
bit is set in the CAN_IMR register.
When one of the error counters values exceeds 96, an increased error rate is indicated to the
controller through the WARN bit in CAN_SR register, but the node remains error active. The
corresponding interrupt is pending while the interrupt is set in the CAN_IMR register.
Refer to the Bosch CAN specification v2.0 for details on fault confinement.
39.6.4.3 Overload
The overload frame is provided to request a delay of the next data or remote frame by the
receiver node (“Request overload frame”) or to signal certain error conditions (“Reactive over-
load frame”) related to the intermission field respectively.
Reactive overload frames are transmitted after detection of the following error conditions:
• Detection of a dominant bit during the first two bits of the intermission field
• Detection of a dominant bit in the last bit of EOF by a receiver, or detection of a dominant
bit by a receiver or a transmitter at the last bit of an error or overload frame delimiter
The CAN controller can generate a request overload frame automatically after each message
sent to one of the CAN controller mailboxes. This feature is enabled by setting the OVL bit in
the CAN_MR register.
ERROR
ACTIVE
ERROR
PASSIVE
BUS OFF
TEC > 255
Init
TEC > 127
or
REC > 127
TEC < 127
and
REC < 127
128 occurences of 11 consecutive recessive bits
or
CAN controller reset