Freescale Semiconductor MCF5480 - Manual (Page 514)

MCF548x Reference Manual, Rev. 3
19-30 Freescale Semiconductor
NOTE
Registers MBAR + 0x8420 through MBAR + 0x843C are reserved for
future use. Accesses to these registers will result in undefined behavior.
23 BE3 Bus error type 3. This bit is set whenever a slave bus transaction attempts to write to a Read-Only
register. This flag bit is set regardless of the bus error enable bit (BE). If software is polling and
wishes to disregard this error it must mask this bit out. No register bit corruption occurs for this (or
any other) bus error case. This bit is cleared by writing ‘1’ to it.
22 BE2 Bus error type 2. This bit is set whenever a slave bus transaction attempts to write to a Reserved
register (an entire 32-bit register, not just a Reserved bit or byte). This flag bit is set regardless of
the bus error enable bit (BE). If software is polling and wishes to disregard this error it must mask
this bit out. This bit is cleared by writing ‘1’ to it.
21 BE1 Bus error type 1. This bit is set whenever a slave bus transaction attempts to read a Reserved
register (an entire 32-bit register, not just a Reserved bit or byte). This flag bit is set regardless of
the bus error enable bit (BE). If software is polling and wishes to disregard this error it must mask
this bit out. This bit is cleared by writing ‘1’ to it.
20 FE FIFO error. This bit is set whenever the Transmit FIFO asserts an unmasked error bit. An interrupt
will be generated by this condition if the PCITER[FEE] bit is set. The source of the error must be
determined by reading the FIFO status register PCITFSR. Also, the error condition must be cleared
at the FIFO prior to clearing this Sticky bit or this flag will continue to assert. This bit is cleared by
writing ‘1’ to it.
19 SE System error. This bit is set in response to the Transmit Controller entering an illegal state. System
error indicates a malfunction of the block and should not occur in normal operation. An interrupt
can be generated by this condition if the PCITER[SE] bit is set. In normal operation this should
never occur. The only recovery is to assert the reset controller bit, PCITER[RC], and clear this flag
by writing ‘1’ to it.
18 RE Retry error. This bit is set if Max_Retries is set to a finite value (0x01 to 0xff) and the PCI transaction
has performed retries in excess of the setting. An interrupt will be generated by this condition if the
PCITER[RE] bit is set. This retry counter is reset at the beginning of each packet, not at the
beginning of each transaction.This bit is cleared by writing ‘1’ to it.
17 TA Target abort. This bit is set if the PCI controller has issued a Target Abort (which means the
addressed PCI Target has signalled an Abort). An interrupt will be generated by this condition if the
PCITER[TAE] bit is set. It is up to application software to query the Target’s status register and
determine the source of the error. The coherency of the Transmit FIFO data and the Transmit
Controller’s status registers (Next_Address, Bytes_Done, etc.) should remain valid. This bit is
cleared by writing ‘1’ to it.
16 IA Initiator abort. This bit is set if the PCI controller issues an Initiator Abort. This indicates that no
Target responded but further status information can be read from the PCI Configuration interface.
An interrupt will be generated by this condition if the PCITER[IAE] bit is set. The coherency of the
Transmit FIFO data and the Transmit Controller’s status registers (Next_Address, Bytes_Done,
etc.) should remain valid.This bit is cleared by writing ‘1’ to it.
15–0 — Reserved, should be cleared.
Table 19-26. PCITSR Field Descriptions (Continued)
Bits Name Description