Freescale Semiconductor MCF5480 - Manual (Page 12)

MCF548x Reference Manual, Rev. 3
xii Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
6.2.3.5 Denormalized Numbers .......................................................................................... 6-5
6.3 Register Definition .......................................................................................................... 6-7
6.3.1 Floating-Point Data Registers (FP0–FP7) .................................................................. 6-7
6.3.2 Floating-Point Control Register (FPCR) .................................................................... 6-7
6.3.3 Floating-Point Status Register (FPSR) ....................................................................... 6-9
6.3.4 Floating-Point Instruction Address Register (FPIAR) .............................................. 6-10
6.4 Floating-Point Computational Accuracy ...................................................................... 6-11
6.4.1 Intermediate Result ................................................................................................... 6-11
6.4.2 Rounding the Result .................................................................................................. 6-12
6.5 Floating-Point Post-Processing ..................................................................................... 6-14
6.5.1 Underflow, Round, and Overflow ............................................................................ 6-14
6.5.2 Conditional Testing ................................................................................................... 6-15
6.6 Floating-Point Exceptions ............................................................................................. 6-17
6.6.1 Floating-Point Arithmetic Exceptions ...................................................................... 6-18
6.6.1.1 Branch/Set on Unordered (BSUN) ....................................................................... 6-19
6.6.1.2 Input Not-A-Number (INAN) ............................................................................... 6-20
6.6.1.3 Input Denormalized Number (IDE) ...................................................................... 6-20
6.6.1.4 Operand Error (OPERR) ....................................................................................... 6-21
6.6.1.5 Overflow (OVFL) ................................................................................................. 6-21
6.6.1.6 Underflow (UNFL) ............................................................................................... 6-22
6.6.1.7 Divide-by-Zero (DZ) ............................................................................................ 6-22
6.6.1.8 Inexact Result (INEX) .......................................................................................... 6-23
6.6.2 Floating-Point State Frames ...................................................................................... 6-23
6.7 Instructions .................................................................................................................... 6-25
6.7.1 Floating-Point Instruction Overview ........................................................................ 6-25
6.7.2 Floating-Point Instruction Execution Timing ........................................................... 6-27
6.7.3 Key Differences between ColdFire and M68000 FPU Programming Models ......... 6-28
Chapter 7
Local Memory
7.1 Interactions between Local Memory Modules ............................................................... 7-1
7.2 SRAM Overview ............................................................................................................ 7-1
7.3 SRAM Operation ............................................................................................................ 7-2
7.4 SRAM Register Definition ............................................................................................. 7-2
7.4.1 SRAM Base Address Registers (RAMBAR0/RAMBAR1) ....................................... 7-2
7.5 SRAM Initialization ........................................................................................................ 7-4
7.5.1 SRAM Initialization Code .......................................................................................... 7-5
7.6 Power Management ........................................................................................................ 7-6
7.7 Cache Overview .............................................................................................................. 7-6
7.8 Cache Organization ......................................................................................................... 7-7