Freescale Semiconductor MCF5480 - Manual (Page 214)

MCF548x Reference Manual, Rev. 3
6-24 Freescale Semiconductor
Note that if no intervention is needed, instead of FSAVE, the handler can simply clear the appropriate
FPCR and FPSR bits and then return from the exception.
Because the FPCR and FPSR are written in the FSAVE frame, a context switch needs only execute FSAVE
and FMOVEM for data registers. The new process needs to load data registers by using a
FMOVEM/FRESTORE sequence before it can continue.
FSAVE operations always write a 4-longword floating-point state frame that holds a 64-bit exception
operand. Figure 6-13 shows FSAVE frame contents.
Figure 6-13. Floating-Point State Frame Contents
Table 6-22 describes format word fields.
When FSAVE executes, the floating-point frame reflects the FPU state at the time of the FSAVE.
Internally, the FPU can be in the NULL, IDLE, or EXCP states. Upon reset, the FPU is in NULL state, in
which all floating-point registers contain NANs and the FPCR, FPSR, and FPIAR contain zeros. The FPU
remains in NULL state until execution of an implemented floating-point instruction (except FSAVE). At
this point, the FPU transitions from NULL to an IDLE state. A FRESTORE of NULL returns the FPU to
NULL state.
EXCP state is entered as a result of a floating-point exception or an unsupported data type exception. The
vector field identifies exception types associated with the EXCP state. This field and the exception vector
taken are determined directly from the exception control (FPCR) and status (FPSR) bits. An FSAVE
instruction always clears FPCR after saving its state. Thus, after an FSAVE, a handler does not generate
further floating-point exceptions unless the handler re-enables the exceptions. FRESTORE returns FPCR
and FPSR to their previous state before entering the handler, as stored in the state frame. A handler could
alter the state frame to restore the FPU (using FRESTORE) into a different state than that saved by using
FSAVE.
31 24 23 19 18 16 15 0
Format word Control Register (FPCR)
Frame Format 0000_0 Vector
Exception operand upper 32 bits
Exception operand lower 32 bits
Status register (FPSR)
Table 6-22. Format Word Field Descriptions
Bits Name Description
31–24 Frame
format Defines the format of the frame.
0x00 Null Frame (NULL)
0x05 Idle Frame (IDLE)
0xE5 Exception Frame (EXCP)
23–19 — Zeros
18–16 Vector Exception vector
000 BSUN
001 INEX
010 DZ
011 UNFL
100 OPERR
101 OVFL
110 INAN
111 IDE