Freescale Semiconductor MCF5480 - Manual (Page 435)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 17-19
Figure 17-14 illustrates the basic byte read transfer to an 8-bit device with no wait states. The address is
driven on the full AD[31:0] bus in the first clock. The MCF548x tristates AD[31:24] on the second clock
and continues to drive address on AD[23:0] throughout the bus cycle. The external device returns the read
data on AD[31:24], and may tristate the data line or continue to drive the data one clock after TA is sampled
asserted.
Figure 17-14. Single Byte Read Transfer with Muxed 32-A / 8-D
or Non-Muxed 24-A / 8-D
Figure 17-15 shows the similar configuration for a write transfer. The data is driven from the second clock
on AD[31:24].
CLK
S0 S1 S2 S3
AD[31:24]
R/W
ALE
TA
OE
FBCSn, BE/BWEn
AD[15:8]
AD[7:0]
AD[23:16] ADDR[23:16]
A[31:24] D[7:0]
ADDR[15:8]
ADDR[7:0]
TSIZ[1:0] 01