Freescale Semiconductor MCF5480 - Manual (Page 626)

MCF548x Reference Manual, Rev. 3
22-24 Freescale Semiconductor
18 SRD Secondary EU reset done. Reflects the state of the reset done signal from the assigned
secondary EU.
0 The assigned secondary EU reset done signal is inactive.
1 The assigned secondary EU reset done signal is active indicating its reset sequence has
completed and it is ready to accept data.
17 PD Primary EU done. Reflects the state of the done interrupt from the assigned primary EU.
0 The assigned primary EU done interrupt is inactive.
1 The assigned primary EU done interrupt is active indicating the EU has completed
processing and is ready to provide output data.
16 SD Secondary EU done. Reflects the state of the done interrupt from the assigned secondary EU.
0 The assigned secondary EU done interrupt is inactive.
1 The assigned secondary EU done interrupt is active indicating the EU has completed
processing and is ready to provide output data.
15–14 — Reserved, should be cleared.
13 TEA Transfer error acknowledge. When the SEC is a bus master and detects a TEA, the controller
passes the TEA to the channel in use. The channel halts and outputs an interrupt. The channel
can only be restarted by resetting the channel or the entire SEC.
0 No error.
1 Transfer error acknowledge received from the bus interface.
12 PERR Pointer not complete error. Caused by an invalid write to the next descriptor register in the
descriptor buffer, or to the fetch register.
0 No error.
1 Pointer not complete error.
11 — Reserved, should be cleared.
10 DERR Descriptor error. The channel has detected an illegal descriptor header.
0 No error.
1 Descriptor error.
9 SERR Static assignment error. Either the EU is statically assigned to a different channel or the
dynamic assignment request cannot be filled because all suitable EUs are otherwise statically
assigned.
0 No error.
1 Static assignment error.
Table 22-14. CCPSRLn Field Descriptions (Continued)
Bits Name Description