Freescale Semiconductor MCF5480 User Manual
Page 635
ARC Four Execution Unit (AFEU)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
22-33
Figure 22-24. AFEU Interrupt Mask Register (AFIMR)
describes AFEU interrupt mask register fields.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
ME
AE
OFE
IFE
0
IFO
OFU
0
0
0
0
IE
ERE
CE
KSE
DSE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x28038
Table 22-21. AFIMR Field Descriptions
Bits
Names
Description
31
ME
Mode Error. An illegal value was detected in the mode register.
0 Mode error enabled
1 Mode error disabled
30
AE
Address Error. An illegal read or write address was detected within the AFEU address
space.
0 Address error enabled
1 Address error disabled
29
OFE
Output FIFO Error. The AFEU Output FIFO was detected non-empty upon write of AFEU
data size register
0 Output FIFO non-empty error enabled
1 Output FIFO non-empty error disabled
28
IFE
Input FIFO Error. The AFEU Input FIFO was detected non-empty upon generation of done
interrupt.
0 Input FIFO non-empty error enabled
1 Input FIFO non-empty error disabled
27
—
Reserved
26
IFO
Input FIFO Overflow. The AFEU Input FIFO has been pushed while full.
0 Input FIFO overflow error enabled
1 Input FIFO overflow error disabled
25
OFU
Output FIFO Underflow. The AFEU Output FIFO has been read while empty.
0 Output FIFO underflow error enabled
1 Output FIFO underflow error disabled
24–21
—
Reserved
20
IE
Internal Error. An internal processing error was detected while performing encryption.
0 Internal error enabled
1 Internal error disabled