Freescale Semiconductor MCF5480 - Manual (Page 443)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 17-27
NOTE
Line-sized transfers requested by the core or cache are broken up into four
individual longword transfers, but the DMA can request line-sized transfers
when the read line or combine write flags are set. See Section 24.4.9, “Line
Buffers,” for more information.
CSCRs are used to enable bursting for reads, writes, or both. Memory spaces can be declared
burst-inhibited for reads and writes by clearing the appropriate CSCRn[BSTR,BSTW].
Figure 17-27 shows a longword read through an 8-bit device programmed for burst enable. The transfer
results in a 4-beat burst and the data is driven on AD[31:24]. Notice that the transfer size is driven at
longword (2’b00) throughout the bus cycle.
Figure 17-27. Longword Read Burst from 8-Bit Port 3-1-1-1 (No Wait States)
Figure 17-28 shows a longword write through an 8-bit device programmed for burst enable. The transfer
results in a 4-beat burst and the data is driven on AD[31:24]. Notice that the transfer size is driven at
longword (2’b00) throughout the bus cycle.
CLK
AD[23:0]
AD[31:24]
R/W
ALE
TA
OE
S0 S1 S2 S2 S2 S2 S3
FBCSn, BE/BWEn
ADDR[23:0]
A[31:24] DATA DATA DATA DATA
TSIZ[1:0] 00
TBST