Freescale Semiconductor MCF5480 - Manual (Page 13)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor xiii
Contents
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Number
Title
Page
Number
7.8.1 Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified ......................... 7-8
7.8.2 The Cache at Start-Up ................................................................................................. 7-8
7.9 Cache Operation ........................................................................................................... 7-10
7.9.1 Caching Modes ......................................................................................................... 7-12
7.9.1.1 Cacheable Accesses .............................................................................................. 7-12
7.9.1.2 Cache-Inhibited Accesses ..................................................................................... 7-13
7.9.2 Cache Protocol .......................................................................................................... 7-14
7.9.2.1 Read Miss ............................................................................................................. 7-14
7.9.2.2 Write Miss (Data Cache Only) ............................................................................. 7-14
7.9.2.3 Read Hit ................................................................................................................ 7-15
7.9.2.4 Write Hit (Data Cache Only) ................................................................................ 7-15
7.9.3 Cache Coherency (Data Cache Only) ....................................................................... 7-15
7.9.4 Memory Accesses for Cache Maintenance ............................................................... 7-15
7.9.4.1 Cache Filling ......................................................................................................... 7-15
7.9.4.2 Cache Pushes ........................................................................................................ 7-16
7.9.5 Cache Locking .......................................................................................................... 7-17
7.10 Cache Register Definition ............................................................................................. 7-19
7.10.1 Cache Control Register (CACR) .............................................................................. 7-19
7.10.2 Access Control Registers (ACR0–ACR3) ................................................................ 7-22
7.11 Cache Management ....................................................................................................... 7-23
7.12 Cache Operation Summary ........................................................................................... 7-26
7.12.1 Instruction Cache State Transitions .......................................................................... 7-26
7.12.2 Data Cache State Transitions .................................................................................... 7-27
7.13 Cache Initialization Code .............................................................................................. 7-30
Chapter 8
Debug Support
8.1 Introduction ..................................................................................................................... 8-1
8.1.1 Overview ..................................................................................................................... 8-1
8.2 Signal Descriptions ......................................................................................................... 8-2
8.2.1 Processor Status/Debug Data (PSTDDATA[7:0]) ..................................................... 8-3
8.3 Real-Time Trace Support ................................................................................................ 8-5
8.3.1 Begin Execution of Taken Branch (PST = 0x5) ......................................................... 8-6
8.3.2 Processor Stopped or Breakpoint State Change (PST = 0xE) .................................... 8-7
8.3.3 Processor Halted (PST = 0xF) .................................................................................... 8-8
8.4 Memory Map/Register Definition .................................................................................. 8-9
8.4.1 Revision A Shared Debug Resources ....................................................................... 8-11
8.4.2 Configuration/Status Register (CSR) ........................................................................ 8-11
8.4.3 PC Breakpoint ASID Control Register (PBAC) ....................................................... 8-14
8.4.4 BDM Address Attribute Register (BAAR) ............................................................... 8-15