Freescale Semiconductor MCF5480 - Manual (Page 263)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 8-13
18 BKD Breakpoint disable. Used to disable the normal BKPT input functionality and to allow the assertion
of BKPT to generate a debug interrupt.
0 Normal operation
1 BKPT is edge-sensitive: a high-to-low edge on BKPT signals a debug interrupt to the processor.
The processor makes this interrupt request pending until the next sample point, when the
exception is initiated. In the ColdFire architecture, the interrupt sample point occurs once per
instruction. There is no support for nesting debug interrupts.
17 PCD PSTCLK disable. Setting PCD disables generation of PSTCLK and PSTDDATA outputs and forces
them to remain quiescent.
16 IPW Inhibit processor writes. Setting IPW inhibits processor-initiated writes to the debug module’s
programming model registers. IPW can be modified only by commands from the external
development system.
15 MAP Force processor references in emulator mode.
0 All emulator-mode references are mapped into supervisor code and data spaces.
1 The processor maps all references while in emulator mode to a special address space, TT = 10,
TM = 101 or 110. The internal SRAM and caches are disabled.
14 TRC Force emulation mode on trace exception. If TRC = 1, the processor enters emulator mode when a
trace exception occurs. If TRC=0, the processor enters supervisor mode.
13 EMU Force emulation mode. If EMU = 1, the processor begins executing in emulator mode. See
Section 8.6.1.1, “Emulator Mode .”
12–11 DDC Debug data control. Controls operand data capture for PSTDDATA, which displays the number of
bytes defined by the operand reference size before the actual data; byte displays 8 bits, word
displays 16 bits, and long displays 32 bits (one nibble at a time across multiple clock cycles). See
Table 8-4 .
00 No operand data is displayed.
01 Capture all write data.
10 Capture all read data.
11 Capture all read and write data.
10 UHE User halt enable. Selects the CPU privilege level required to execute the HALT instruction.
0 HALT is a supervisor-only instruction.
1 HALT is a supervisor/user instruction.
9–8 BTB Branch target bytes. Defines the number of bytes of branch target address PSTDDATA displays.
00 0 bytes
01 Lower 2 bytes of the target address
10 Lower 3 bytes of the target address
11 Entire 4-byte target address
See
Section 8.3.1, “Begin Execution of Taken Branch (PST = 0x5) .”
7 — Reserved, should be cleared.
Table 8-8. CSR Field Descriptions (Continued)
Bits Name Description